Method of manufacturing semiconductor optical device and semiconductor optical device

ABSTRACT

Provided is a method of manufacturing a semiconductor optical device, which makes it possible to reduce the thickness of a semiconductor optical device including InGaAsP-based III-V compound semiconductor layers containing at least In and P to a thickness smaller than that of conventional devices, and provide a semiconductor optical device. The method of manufacturing a semiconductor optical device includes a step of forming a semiconductor laminate  30  on the InP growth substrate; a step of bonding the semiconductor laminate  30  to the support substrate  80  formed from a Si substrate, with at least the metal bonding layer  70  therebetween; and a step of removing the InP growth substrate  10.

TECHNICAL FIELD

This disclosure relates to a method of manufacturing a semiconductoroptical device and a semiconductor optical device

BACKGROUND

Conventionally, semiconductor optical devices which emit or receivelight in the infrared region are known, such as infrared emissionsemiconductor light-emitting diodes which emit light with a wavelengthof 750 nm or more in the infrared region, and infrared rangesemiconductor light receiving devices which detect light withwavelengths in the infrared region. For example, infrared emissionsemiconductor light-emitting diodes are widely used in the applicationssuch as sensors, gas analysis, and surveillance cameras.

When reception or emission wavelengths of such a semiconductor opticaldevice are 1000 nm to 2200 nm in the near infrared region, a p-njunction area formed from an InGaAsP-based III-V semiconductorcontaining In and P is usually formed. Conventionally, when anInGaAsP-based III-V semiconductor layer such as an InP layer isepitaxially grown, an InP substrate is used as a growth substrate sothat the growth substrate and the InGaAsP-based III-V semiconductorlayer containing In and P are lattice matched.

For example, JP H07-147454 A (PTL 1) discloses a semiconductor laserdiode emitting at wavelengths in the 1.3 μm range. This semiconductorlaser has a strained multiple quantum well active layer formed on ann-type InP substrate, and the strained multiple quantum well activelayer has a structure in which InGaAsP strained quantum wells andInGaAsP barrier layers are alternately stacked.

Further, JP H06-237042 A (PTL 2) describes that InGaAsP barrier layershaving the same lattice constant as an InP substrate, and quantum welllayers including strained quantum well layers each formed from anIn_(0.3)Ga_(0.7)As layer having a smaller lattice constant than the InPsubstrate and lattice strain compensation layers each formed of InAshaving a larger lattice constant than the InP substrate are provided onthe InP substrate.

Further, JP 2001-156324 A (PTL 3) discloses a near infrared rangesemiconductor light receiving device in which an InAsP buffer layer isformed on an InP substrate, an InGaAs light absorption layer having thesame lattice constant as the InP substrate is formed on the bufferlayer, and an InAsP window layer is formed on the light absorptionlayer.

CITATION LIST Patent Literature

PTL 1: JP H07-147454 A

PTL 2: JP H06-237042 A

PTL 3: JP 2001-156324 A

SUMMARY Technical Problem

In each of the techniques described in PTL 1, PTL 2, and PTL 3, the InPsubstrate as the growth substrate is used directly as a supportsubstrate of the semiconductor optical device. This does not affecttransparency to infrared light, since the InP substrate is transparentto light in the near infrared region.

In recent years, there is a demand for smaller semiconductor opticaldevices which receives or emits light in the infrared region, withincrease in demand for wearable devices. In particular, there is anincreasing demand for semiconductor optical devices to have a smallerthickness (i.e., devices having a smaller total thickness).

Here, the thickness of a commercially available InP substrate istypically 350 μm or more for a 2 in substrate. On the other hand, thethickness of an InGaAsP-based III-V semiconductor layer, an electrode,etc. provided other than the InP substrate in a semiconductor opticaldevice is several micrometers at most. Accordingly, a substratedominates a semiconductor optical device in thickness. The inventors ofthis disclosure contemplated epitaxially growing an InGaAsP-based III-Vsemiconductor layer on an InP substrate and then grinding the InPsubstrate by ⅓ or more of the original thickness. However, since an InPsubstrate is brittle, the InP substrate would be broken if the InPsubstrate is excessively ground to less than 200 μm, for example 150 μmor less. Therefore, the thickness of a near infrared range semiconductoroptical device could not be reduced sufficiently.

Given these circumstances, it could be helpful to provide a method ofmanufacturing a semiconductor optical device, which makes it possible toreduce the thickness of a semiconductor optical device includingInGaAsP-based III-V compound semiconductor layers containing at least Inand P to a thickness smaller than that of conventional devices, and toprovide a semiconductor optical device.

Solution to Problem

The inventors of this disclosure diligently studied ways to address theabove problems, and conceived a bonding process method. Then theycontemplated removing an InP growth substrate using an Si substratewhich can be made thin to serve as a support substrate. This idea led todisclosure.

Specifically, we propose the following features.

(1) A method of manufacturing a semiconductor optical device,comprising:

a step of forming a semiconductor laminate in which a plurality ofInGaAsP-based III-V compound semiconductor layers containing at least Inand P are stacked, on an InP growth substrate;

a step of bonding the semiconductor laminate to a conductive supportsubstrate formed from a Si substrate with at least a metal bonding layertherebetween; and a step of removing the InP growth substrate.

(2) The method of manufacturing a semiconductor optical device,according to (1) above, further comprising a grinding step of grindingthe conductive support substrate to a thickness in a range of 80 μm ormore and less than 200 μm.(3) A method of manufacturing a semiconductor optical device,comprising:

a first step of forming a semiconductor laminate in which a plurality ofInGaAsP-based III-V compound semiconductor layers containing at least Inand P are stacked, on an InP growth substrate;

a second step of forming a contact layer formed of a III-V compoundsemiconductor on the semiconductor laminate;

a third step of forming an ohmic metal portion on part of the contactlayer leaving an exposed area on a surface of the contact layer;

a fourth step of removing the contact layer of the exposed area so thata surface of the semiconductor laminate is exposed, thereby forming acontact portion composed of the ohmic metal portion and the contactlayer and forming an exposed surface of the semiconductor laminate;

a fifth step of forming a dielectric layer on at least part of theexposed surface of the semiconductor laminate;

a sixth step of forming a reflective metal layer mainly containing Au onthe dielectric layer and the contact portion;

a seventh step of bonding a conductive support substrate having asurface provided with a metal bonding layer to the reflective metallayer with the metal bonding layer therebetween; and

an eighth step of removing the InP growth substrate,

wherein the support substrate is a conductive Si substrate.

(4) The method of manufacturing a semiconductor optical device,according to (3) above, further comprising a grinding step of grindingthe conductive support substrate to a thickness in a range of 80 μm ormore and less than 200 μm.(5) The method of manufacturing a semiconductor optical device,according to (3) or (4) above, wherein the semiconductor laminateincludes an n-type cladding layer, an active layer, and a p-typecladding layer in this order, and

the n-type cladding layer, the active layer, and the p-type claddinglayer are layers formed of an InGaAsP-based III-V compound semiconductorcontaining at least In and P.

(6) The method of manufacturing a semiconductor optical device,according to (5) above, wherein the semiconductor laminate has one of adouble heterostructure and a multiple quantum-well structure.(7) The method of manufacturing a semiconductor optical device,according to any one of claims 3 to 6, wherein the dielectric layer isformed of SiO₂.(8) A semiconductor optical device comprising:

a conductive support substrate formed from a Si substrate;

a metal bonding layer provided on a surface of the conductive supportsubstrate; and

a semiconductor laminate in which a plurality of InGaAsP-based III-Vcompound semiconductor layers containing at least In and P are stacked,the semiconductor laminate being provided on the metal bonding layer.

(9) The semiconductor optical device according to (8) above, wherein athickness of the conductive support substrate is in a range of 80 μm ormore and less than 200 μm.(10) A semiconductor optical device comprising:

a conductive support substrate;

a metal bonding layer provided on a surface of the conductive supportsubstrate;

a reflective metal layer provided on the metal bonding layer;

a semiconductor laminate in which a plurality of InGaAsP-based III-Vcompound semiconductor layers containing at least In and P are stacked,the semiconductor laminate being provided on the reflective metal layer;and

a dielectric layer and a contact portion that are provided in parallelbetween the reflective metal layer and the semiconductor laminate,

the reflective metal layer mainly contains Au, and

the conductive support substrate is formed from a conductive Sisubstrate.

(11) The semiconductor optical device according to (10) above, wherein athickness of the conductive support substrate is in a range of 80 μm ormore and less than 200 μm.(12) The semiconductor optical device according to (10) or (11) above,wherein the semiconductor laminate includes an n-type cladding layer, anactive layer, and a p-type cladding layer in this order, and

the n-type cladding layer, the active layer, and the p-type claddinglayer are layers formed of an InGaAsP-based III-V compound semiconductorcontaining at least In and P.

(13) The semiconductor optical device according to (12) above, whereinthe semiconductor laminate has one of a double heterostructure and amultiple quantum-well structure.(14) The semiconductor optical device, according to any one of (10) to(13) above, wherein the dielectric layer is formed of SiO₂.

Advantageous Effect

This disclosure can provide a method of manufacturing a semiconductoroptical device, which makes it possible to reduce the thickness of asemiconductor optical device including InGaAsP-based III-V compoundsemiconductor layers containing at least In and P to a thickness smallerthan that of conventional devices, and provide a semiconductor opticaldevice.

BRIEF DESCRIPTION OF THE DRAWINGS

In the accompanying drawings,

FIG. 1 presents schematic cross-sectional views illustrating Steps 1A to1C of a manufacturing process of a semiconductor light-emitting diodeaccording to a first embodiment of this disclosure;

FIG. 2 presents schematic cross-sectional views illustrating Steps 2A to2C of the manufacturing process of a semiconductor light-emitting diodeaccording to the first embodiment of this disclosure;

FIG. 3 presents schematic cross-sectional views illustrating Steps 3Aand 3B of the manufacturing process of a semiconductor light-emittingdiode according to the first embodiment of this disclosure;

FIG. 4 presents schematic cross-sectional views illustrating Steps 4Aand 4B of the manufacturing process of a semiconductor light-emittingdiode according to the first embodiment of this disclosure;

FIG. 5 is a schematic view illustrating the periphery of a dielectriclayer and a contact portion of a semiconductor light-emitting diodeaccording to a preferred aspect of the first embodiment of thisdisclosure;

FIG. 6 presents schematic cross-sectional views illustrating Steps 6A to6E of a manufacturing process of a semiconductor optical deviceaccording to a third embodiment of this disclosure;

FIG. 7A is a schematic top view illustrating a pattern of an ohmicelectrode portion of Examples, and FIG. 7B is a schematic top viewillustrating a pattern of a top electrode of Examples; and

FIG. 8A is a graph depicting a light distribution pattern of Example 1,and FIG. 8B is a graph depicting a light distribution pattern ofConventional Example 1.

DETAILED DESCRIPTION

Prior to describing embodiments of this disclosure, the following pointsare described beforehand. First, in this specification, the expression“InGaAsP” alone for which the composition ratio is not specified means agiven compound having a chemical composition ratio of group III elements(In and Ga in total) with respect to group V elements (As and P) of 1:1,in which the ratio between In and Ga that are group III elements and theratio between As and P that are group V elements are undefined. In thiscase, there may be a possibility that one of In and G is not containedas the group III elements; or there may be a possibility that one of Asand P is not contained as the group V elements. However, InGaAsPspecified as “containing at least In and P” means that more than 0% and100% or less of In is contained in the group III elements, and 0% and100% or less of P is contained in the group V elements. Further, theexpression “InGaP” means that As is not contained in “InGaAsP” above,and the expression “InGaAs” means that P is not contained in “InGaAsP”above. Similarly, the expression “InAsP” means that Ga is not containedin “InGaAsP” above, and the expression “GaAsP” means that In is notcontained in “InGaAsP” above. Further, the expression “InP” means thatGa and As are not contained in “InGaAsP” above. Note that the ratiobetween the components of InGaAsP can be measured for example by aphotoluminescence measurement or an X-ray diffraction measurement.

In this specification, a layer serving as an electrically p-type layeris referred to as a p-type layer, and a layer serving as an electricallyn-type layer is referred to as an n-type layer. Meanwhile, a layer thatis not intentionally doped with certain impurities such as Zn, S, and Snand does not serve as an electrically p-type or n-type layer is referredto as an “i-type” or “undoped” layer. An undoped InGaAsP layer maycontain impurities that are inevitably mixed in the production process.Specifically, when the carrier density is low (for example, less than4×10¹⁶/cm³), the layer is handled as being “undoped” in thisspecification. Further, the values of the impurity concentrations of Zn,Sn, etc. are determined by SIMS analysis.

The total thickness of the layers formed can be measured using athickness measurement system using optical interferometry. Moreover, thethickness of each layer can be calculated by observing a cross sectionof the growth layer using a thickness measurement system using opticalinterferometry and a transmission electron microscope. When thethickness of each layer is small as in a superlattice structure, thethickness can be measured using TEM-EDS. Note that when a certain layerhas an inclined surface in a cross-sectional view, the thickness of thelayer is defined by the maximum height of the layer from a flat surfaceof the underlying layer.

A semiconductor optical device of this disclosure may take two forms: asemiconductor light-emitting diode and a semiconductor light receivingdevice. First, a semiconductor light-emitting diode of the firstembodiment will be described with reference to the drawings. Prior todescribing an embodiment of the method of manufacturing a semiconductorlight-emitting diode according to the first embodiment, the relationshipbetween FIG. 1 to FIG. 5 is described beforehand. FIG. 1 to FIG. 4present schematic cross-sectional views illustrating steps of a methodof manufacturing a semiconductor light-emitting diode according to thefirst embodiment of this disclosure. This semiconductor light-emittingdiode can be manufactured in the order of Steps 1A to 1C in FIG. 1,Steps 2A to 2C in FIG. 2, Steps 3A and 3B in FIG. 3, and Steps 4A and 4Bin FIG. 4. FIG. 5 is an enlarged view of the periphery of a dielectriclayer 50 and a contact portion 40 of a preferred aspect which arepreferably formed in Step 2C of FIG. 2. In principle, components thatare identical or corresponding to each other are herein denoted by thesame reference numerals, and thus a description thereof will not berepeated also in the embodiment to be described with reference to FIG.6. A substrate and layers in each diagram are exaggerated in width andthickness for convenience of description, so that the ratio between thevertical and horizontal dimensions of each illustrated component doesnot conform to the actual ratio.

First Embodiment: Method of Manufacturing Semiconductor Light-EmittingDiode

A method of manufacturing a semiconductor light-emitting diode 100,according to the first embodiment of this disclosure has a first step, asecond step, a third step, a fourth step, a fifth step, a sixth step, aseventh step, and an eighth step to be described in detail below. In thefirst step, a semiconductor laminate 30 in which a plurality ofInGaAsP-based III-V compound semiconductor layers containing at least Inand P are stacked is formed on an InP growth substrate 10 (Steps 1A and1B in FIG. 1). In the second step, a contact layer 41 formed of a III-Vcompound semiconductor is formed on the semiconductor laminate 30 (Step1C in FIG. 1). In the third step, an ohmic metal portion 43 is formed onpart of the contact layer 41 leaving an exposed area E1 on a surface ofthe contact layer 41 (Step 2A in FIG. 2). In the fourth step, thecontact layer 41 of the exposed area E1 is removed so that a surface ofthe semiconductor laminate 30 is exposed, thereby forming a contactportion 40 composed of the ohmic metal portion 43 and the contact layer41 a and forming an exposed surface E2 of the semiconductor laminate 30(Step 2B in FIG. 2). In the fifth step, a dielectric layer 50 is formedon at least part of the exposed surface E2 of the semiconductor laminate30 (Step 2C in FIG. 2). In the sixth step, a reflective metal layer 60mainly containing Au is formed on the dielectric layer 50 and thecontact portion 40 (Step 3A in FIG. 3). In the seventh step, aconductive support substrate 80 having a surface provided with a metalbonding layer 70 is bonded to the reflective metal layer 60 with themetal bonding layer 70 therebetween (Step 3B in FIG. 3). In the eighthstep, the InP growth substrate 10 is removed (Step 4A in FIG. 4). Here,in this embodiment, the support substrate 80 is a conductive Sisubstrate. Thus, the semiconductor light-emitting diode 100 according tothe first embodiment of this disclosure is manufactured. These stepswill be sequentially described in detail below.

<First Step>

As described above, the first step is a step where the semiconductorlaminate 30 in which a plurality of InGaAsP-based III-V compoundsemiconductor layers containing at least In and P are stacked is formedon the InP growth substrate 10 (Steps 1A and 1B in FIG. 1).

In the first step, as illustrated in Step 1A of FIG. 1, the InP growthsubstrate 10 is first prepared. The InP growth substrate 10 may use anyone of n-type InP substrate, an undoped InP substrate, and a p-type InPsubstrate, which are commercially available. An embodiment using ann-type InP substrate as the InP growth substrate 10 for convenience ofdescription will be described below.

In the first step, the semiconductor laminate 30 in which a plurality ofInGaAsP-based III-V compound semiconductor layers containing at least Inand P are stacked is formed on the InP growth substrate 10. Preferably,the semiconductor laminate 30 includes an n-type cladding layer 31, anactive layer 35, and a p-type cladding layer 37 in this order, and then-type cladding layer 31, the active layer 35, and the p-type claddinglayer 37 are layers formed of an InGaAsP-based III-V compoundsemiconductor containing at least In and P. The semiconductor laminate30 may have a double hetero (DH) structure in which the active layer 35is sandwiched between the n-type cladding layer 31 and the p-typecladding layer 37 or may have a multiple quantum well (MQW) structure.With a view to improving the light output power by reducing crystaldefects, the semiconductor laminate 30 more preferably has a multiplequantum-well structure. A multiple quantum-well structure can be formedby alternately repeating well layers 35W and barrier layers 35B. Thewell layers 35W may be of InGaAsP, and the barrier layers 35B arepreferably of InGaAsP having a larger band gap than the well layers 35W.The semiconductor laminate 30 as described above allows thesemiconductor light-emitting diode 100 to emit light having a wavelengthin a desired near-infrared region. For example, an emission peakwavelength of 1000 nm to 1650 nm can be achieved by changing thecomposition of the InGaAsP-based III-V compound. In the case of a MQWstructure, an emission peak wavelength of 1000 nm to 1900 nm can beachieved by in addition to changing the composition of the InGaAsP-basedIII-V compound, applying strain to the well layers by controlling thecomposition difference between the well layers and the barrier layers.As the n-type cladding layer 31, an n-type InP cladding layer ispreferably used, and as the p-type cladding layer 37, a p-type InPcladding layer is preferably used. Further, when the chemicalcomposition of the well layers 35W is expressed asIn_(xw)Ga_(1-xw)As_(yw)P_(1-yw), 0.5≤xw≤1 and 0.5≤yw≤1 can be satisfied,and 0.6≤xw≤0.8 and 0.3≤yw≤1 are preferably satisfied. When the chemicalcomposition of the barrier layers 35B is expressed asIn_(xb)Ga_(1-xb)As_(yb)P_(1-yb), 0.5≤xb≤1 and 0≤yb≤0.5 can be satisfied,and 0.8≤xb≤1 and 0≤yb≤0.2 are preferably satisfied.

The total thickness of the semiconductor laminate 30 may be for example,but not limited to, 2 μm to 8 μm. Similarly, the thickness of the n-typecladding layer 31 may be for example, but not limited to, 1 μm to 5 μm.Further, the thickness of the active layer 35 may be for example, butnot limited to, 100 nm to 1000 nm. Similarly, the thickness of thep-type cladding layer 37 may be for example, but not limited to, 0.8 μmto 3 μm. When the active layer 35 has a quantum well structure, thethickness of the well layers 35W may be 3 nm to 15 nm, and the thicknessof the barrier layers 35B may be 5 nm to 15 nm. The number of pairs ofboth layers may be 3 to 50.

Further, the semiconductor laminate 30 preferably has a p-type cap layer39 formed of InGaAsP containing at least In and P on the p-type claddinglayer 37. The lattice mismatch can be reduced by providing the p-typecap layer 39. The thickness of the cap layer 39 may be for example, butnot limited to, 50 nm to 200 nm. In the following embodiment, forconvenience of description, description is made assuming that theoutermost surface layer of the semiconductor laminate 30 is the p-typecap layer 39; however, since the p-type cap layer 39 is an optionalcomponent, the outermost surface layer of the semiconductor laminate 30may be for example, the p-type cladding layer 37.

Although not shown, the semiconductor laminate 30 preferably has ani-type InP spacer layer each between the n-type cladding layer 31 andthe active layer 35 and between the active layer 35 and the p-typecladding layer. The provision of the i-type InP spacer layers can hinderdopant diffusion. The thickness of the i-type InP spacer layers may befor example, but not limited to, 50 nm to 400 nm.

Here, the layers in the semiconductor laminate 30 can be formed byepitaxial growth, for example by a known thin film deposition techniquesuch as metalorganic chemical vapor deposition (MOCVD), molecular beamepitaxy (MBE), or sputtering. For example, trimethylindium (TMIn) may beused as an In source, trimethylgallium (TMGa) as a Ga source, arsine(AsH₃) as a an As source, and phosphine (PH₃) as a P source at apredetermined mixing ratio, and these source gases may be subjected tovapor phase epitaxy using a carrier gas to form an InGaAsP layer havinga desired thickness by controlling the growth time. Note that otherInGaAsP layers to be epitaxially grown may be formed in a similarmanner. When the layers are p-type or n-type doped, a dopant source gascan be used in addition as desired.

Note that in the first step, before forming the semiconductor laminate30, an etch stop layer 20 is preferably formed on the InP growthsubstrate 10. The etch stop layer 20 can be used when the InP growthsubstrate 10 is removed by etching in the eighth step. The etch stoplayer may use an n-type InGaAs layer, in which case the content of In asa group III element in InGaAs is preferably 0.3 to 0.7, more preferably0.5 to 0.6 so that the etch stop layer can be lattice matched with theInP growth substrate 10.

<Second Step>

As described above, the second step is a step where the contact layer 41formed of a III-V compound semiconductor is formed on the semiconductorlaminate 30 (Step 1C in FIG. 1). For example, as illustrated in Step 1Cof FIG. 1, the p-type contact layer 41 can be formed on the p-type caplayer 39. The p-type contact layer 41 is a layer which is in contactwith the ohmic metal portion 43, is interposed between the ohmic metalportion 43 and the semiconductor laminate 30, and has a compositionallowing for lower contact resistance with the ohmic metal portion 43than with the semiconductor laminate 30. For example, a p-type InGaAslayer can be used as the p-type contact layer 41. The thickness of thecontact layer 41 may be for example, but not limited to, 50 nm to 200nm.

<Third Step>

As described above, the third step is a step where the ohmic metalportion 43 is formed on part of the contact layer 41 leaving the exposedarea E1 on a surface of the contact layer 41 (Step 2A in FIG. 2). Theohmic metal portion 43 can be formed into islands distributed in apredetermined pattern. When a p-type InGaAs layer is used as the p-typecontact layer 41, for example, Au, AuZn, AuBe, AuTi, etc. can be used asthe ohmic metal portion 43, and a structure in which those materials arestacked can preferably be used as the ohmic metal portion 43. Forexample, Au/AuZn/Au (a stack of Au, AuZn, and Au in this order) may beused as the ohmic metal portion 43. The thickness (or the totalthickness) of the ohmic meal portion 43 may be for example, but notlimited to 300 nm to 1300 nm, preferably 350 nm to 800 nm.

Here, for example, the third step can be performed by forming a resistpattern on a surface of the contact layer 41, vapor depositing the ohmicmetal portion 43, and removing the resist pattern by lift-off to obtainthe ohmic metal portion 43. Alternatively, the third step can beperformed by forming a predetermined metal layer on the entire surfaceof the contact layer 41, forming a mask on the metal layer, andperforming for example etching to form the ohmic metal portion 43. Ineither case, as illustrated in Step 2A of FIG. 2, the ohmic metalportion 43 is formed on part of the contact layer 41, the surface of thecontact layer 41 which is not in contact with the ohmic metal portion43, that is, the exposed area E1 is formed.

The shape of the ohmic metal portion 43 may be a trapezoidal shape in across-sectional view in some cases as illustrated in Step 2A of FIG. 2by way of schematic illustration only. The ohmic metal portion 43 may beformed into a rectangular shape or may have rounded corners in across-sectional view.

<Fourth Step>

As described above, the fourth step is a step where the contact layer 41of the exposed area E1 is removed so that a surface of the semiconductorlaminate 30 is exposed, thereby forming the contact portion 40 composedof the ohmic metal portion 43 and the contact layer 41 a and forming theexposed surface E2 of the semiconductor laminate 30 (Step 2B in FIG. 2).Specifically, the contact layer 41 of an area other than the areas ofthe ohmic metal portion 43 formed in the previous third step is etchedto expose a surface of the p-type cap layer 39 which is the outermostsurface layer of the semiconductor laminate 30, thereby obtaining thecontact layer 41 a. For example, a resist mask may be formed on andaround (approximately 2 μm to 5 μm) the ohmic metal portion 43, and theexposed area E1 of the contact layer 41 may be wet etched using tartaricacid-hydrogen peroxide mixture. Alternatively, wet etching may beperformed using inorganic acid-hydrogen peroxide mixture, organicacid-hydrogen peroxide mixture, etc. Further, when a mask is formed on ametal layer and etching is performed to form the ohmic metal portion 43in the third step, the etching of the fourth step can be performed incontinuity with the etching in the third step.

Note that the thickness of the contact portion 40 corresponds to thetotal thickness of the contact layer 41 (41 a) and the ohmic metalportion 43 and may be 350 nm to 1500 nm, more preferably 400 nm to 1000nm.

<Fifth Step>

As described above, the fifth step is a step where the dielectric layer50 is formed on at least part of the exposed surface E2 of thesemiconductor laminate 30 (Step 2C in FIG. 2). Such a dielectric layer50 may be formed for example as follows.

First, a dielectric layer is deposited on the entire surface of thesemiconductor laminate 30 so as to cover the semiconductor laminate 30and the contact portion 40. For the film deposition, a known techniquesuch as plasma CVD or sputtering can be used. When a dielectric on acontact portion is formed in the dielectric layer 50 above the contactportion 40 in the surface of the deposited dielectric layer, a mask maybe formed as desired and the dielectric on the contact portion may beremoved by etching etc. For example, the dielectric on the contactportion may be wet etched using buffered hydrofluoric acid (BHF) or thelike.

Further, as illustrated in FIG. 5, it is also preferred that thedielectric layer 50 is formed on part of the exposed surface E2 of thesemiconductor laminate 30 leaving an exposed portion E3 around thecontact portion 40. The dielectric layer 50 and the exposed portion E3described above may be formed for example as follows. First, adielectric layer is deposited on the entire surface of the semiconductorlaminate 30, and a window pattern completely surrounding the contactportion is formed using resist above the contact portion 40 in thesurface of the deposited dielectric layer. In this case, the windowpattern is preferably 1 μm to 5 μm larger than the contact portion bothin the width direction and the length direction. Using the thus formedresist pattern to remove the dielectric around the contact portion byetching, the dielectric layer 50 can be formed, and the exposed portionE3 is formed around the contact portion 40.

Such an exposed portion E3 is preferably provided, since a heatdissipation path of the semiconductor light-emitting diode 100 isformed. In order to ensure this effect, the width W of the exposedportion E3 is preferably 0.5 μm or more and 5 μm or less, morepreferably 1 μm or more and 3.5 μm or less (see FIG. 5).

Note that the ratio of the area of the dielectric layer 50 in contactwith the semiconductor laminate 30 (contact area ratio) is preferably80% or more 95% or less. When the area of the contact portion 40 isreduced and the area of the dielectric layer 50 is increased, absorptionof light by the contact portion can be reduced. Note that the contactarea ratio can be measured on a wafer, and when the contact area ratiois calculated backwards from the state of singulated semiconductorlight-emitting diodes, the calculation can be performed assuming thatthe width of the semiconductor layer at each end (a region where theelectric layer has been present) removed by singulation is 20 μm to 30μm (40 μm to 60 μm for both ends in total).

Note that in the fifth step, the relationship between the thickness H₁of the dielectric layer 50 and the thickness H₂ of the contact portion40 is not limited in particular; however, as illustrated in FIG. 5, whenthe thickness of the dielectric layer 50 is expressed as H₁ and thethickness of the contact portion is expressed as H₂, H₁≥H₂ can besatisfied, and H₁>H₂ is preferably satisfied. Under these conditions,the thickness of the dielectric layer 50 may be for example, but notlimited to 360 nm to 1600 nm, more preferably 410 nm to 1100 nm.Further, the difference between the thickness H₁ of the dielectric layerand the thickness H₂ of the contact portion 40: H₁-H₂ is preferably 10nm or more and 100 nm or less.

Moreover, the dielectric layer 50 may use SiO₂, SiN, ITO, AlN, etc., andthe dielectric layer 50 is preferably formed of SiO₂ in particular. SiO₂can easily be treated by etching using BHF etc.

<Sixth Step>

As describe above, the sixth step is a step where the reflective metallayer 60 mainly containing Au is formed on the dielectric layer 50 andthe contact portion 40 (Step 3A in FIG. 3). In the fifth step, when theexposed portion E3 is formed, the reflective metal layer 60 is formedalso on the exposed portion E3. The reflective metal layer 60 “mainlycontaining Au” means that Au composes more than 50% by mass in thecomposition of the reflective metal layer 60, and preferably Au composes80% by mass or more. The reflective metal layer 60 may include aplurality of metal layers; however, when it includes a metal layerformed of Au (hereinafter “Au metal layer”), the thickness of the Aumetal layer is preferably more than 50% of the total thickness of thereflective metal layer 60. Other than Au; Al, Pt, Ti, Ag, etc. may beused as metals composing the reflective metal layer 60. For example, thereflective metal layer 60 may be constituted by a single layer formed ofAu only; alternatively, the reflective metal layer 60 may include two ormore Au metal layers. In order to ensure bonding in the subsequentseventh step, the outermost surface layer of the reflective metal layer60 (the surface opposite to the semiconductor laminate 30) is preferablya Au metal layer. For example, metal layers of Al, Au, Pt, and Au may beformed in this order on the dielectric layer 50, the exposed portion E3,and the contact portion 40 to obtain the reflective metal layer 60. Thethickness of one Au metal layer in the reflective metal layer 60 may befor example 400 nm to 2000 nm, and the thickness of each metal layerformed of a metal other than Au may be for example 5 nm to 200 nm. Thereflective metal layer 60 can be formed on the dielectric layer 50, theexposed portion E3, and the contact portion 40 by a typical techniquesuch as a vapor deposition process.

<Seventh Step>

As described above, the seventh step is a step where the conductivesupport substrate 80 having a surface provided with the metal bondinglayer 70 is bonded to the reflective metal layer 60 with the metalbonding layer 70 therebetween (Step 3B in FIG. 3). On a surface of theconductive support substrate 80, the metal bonding layer 70 maypreviously be formed by sputtering, vapor deposition, etc. The metalbonding layer 70 and the reflective metal layer 60 are placed to faceeach other and put together, followed by bonding of the layers bythermocompression bonding at a temperature of approximately 250° C. to500° C.

The metal bonding layer 70 bonded to the reflective metal layer 60 maybe of metals such as Ti, Pt, and Au, or metals forming a eutectic alloywith gold (e.g., Sn), and is preferably formed from a laminate of thosematerials. For example, a laminate obtained by stacking Ti with athickness of 400 nm to 800 nm, Pt with a thickness of 5 nm to 20 nm, andAu with a thickness of 700 nm to 1200 nm in this order on the surface ofthe conductive support substrate 80 can be used as the bonging layer 70.Note that in order to facilitate bonding between the reflective metallayer 60 and the metal bonding layer 70, a Au metal layer is provided asthe outermost surface layer of the metal bonding layer 70, and Au isalso provided as a metal layer of the reflective bonding layer 60 on themetal bonding layer 70 side to perform bonding between Au and Au byAu—Au diffusion bonding.

Here, a conductive Si substrate transparent to near infrared wavelengthsis used as the conductive support substrate 80. A Si substrate hardlybreaks, since it has higher hardness than an InP substrate. Accordingly,as compared with the case of using an InP substrate, the thickness ofthe conductive support substrate 80 can be significantly reduced when aSi substrate is used. Further, a Si substrate is also more advantageousin terms of heat dissipation and cost as compared with an InP substrate.

<Eighth Step>

As described above, the eighth step is a step where the InP growthsubstrate 10 is removed (Step A in FIG. 4). The InP growth substrate 10can be removed by wet etching for example using a hydrochloric aciddiluent, and when the etch stop layer 20 is formed, etching can bestopped by this layer. The etch stop layer being an n-type InGaAs layermay be removed by wet etching for example using sulfuric acid-hydrogenperoxide mixture.

As described above, the semiconductor light-emitting diode 100 can befabricated. This semiconductor light-emitting diode 100 uses aconductive Si substrate as the conductive support substrate 80, so thatthe thickness of the support substrate can be made sufficiently smallerthan the case of using an InP substrate as the support substrate.Accordingly, the total thickness of the semiconductor light-emittingdiode 100 can be made small, thus the semiconductor light-emitting diode100 can be made small. Further, since the reflective metal layer 60 isprovided on the Si substrate of the semiconductor light-emitting diode100, light is emitted from the surface of the diode opposite to the Sisubstrate. On the other hand, in a conventional semiconductorlight-emitting diode in which an InP substrate is used as a growthsubstrate and as a support substrate, light is emitted from both surfaceof the semiconductor laminate and side surfaces thereof. Accordingly,the semiconductor light-emitting diode 100 according to this embodimentis also useful in that the directivity of the emitted light is higherthan the case of conventional semiconductor light-emitting diodes.

Here, although not shown, the manufacturing method according to thisembodiment preferably further includes a grinding step of grinding theconductive support substrate 80 to a thickness in a range of 80 μm ormore and less than 200 μm. In this embodiment, since a Si substrate isused as the conductive support substrate 80, the conductive supportsubstrate 80 would not be broken even if it is ground to a thickness ofless than 200 μm. Further, the conductive support substrate 80 can beground to a thickness of 150 μm or less, or may be ground to a thicknessof 100 μm or less. However, when the conductive support substrate 80 isground to a thickness of less than 80 μm, even a Si substrate would bedamaged. Therefore, the lower limit of the thickness is preferably setto 80 μm. Further, when the thickness of the conductive supportsubstrate 80 is 80 μm or more, the semiconductor light-emitting diode100 is sufficiently handleable.

This grinding step may be performed prior to the above seventh step, maybe performed between the seventh step and the eighth step, or may beperformed after the eighth step. Preferably, the grinding step isperformed after the eighth step. Use of a thinned wafer reduces theprocess step, which prevents the breakage of the wafer more reliably.When the grinding step is performed after the eighth step, the grindingstep is performed before the formation of the back electrode to bedescribed. Note that the grinding of the conductive support substrate 80formed from a Si substrate may be performed by typical mechanicalgrinding, and etching may be performed in addition to the mechanicalgrinding.

The manufacturing method according to this embodiment may further have astep of forming, after the fabrication of the semiconductorlight-emitting diode 100, a back electrode 91 on the back surface of theconductive support substrate 80 and forming a top electrode 93 on thesurface of the semiconductor laminate 30 as illustrated in Step 4B ofFIG. 4. The top electrode 93 may include a wiring portion 93 a and a padportion 93 b. Through such steps, a semiconductor light-emitting diode100′ can be fabricated. The back electrode 91 and the top electrode 93can be formed by a known technique; for example, sputtering,electron-beam physical vapor deposition, resistance heating, etc. can beused.

Further, since an n-type InP substrate is used as the InP growthsubstrate 10 in this embodiment for convenience of description, thelayers formed on the InP growth substrate 10 have n-type and p-typeconductivity types as described above. On the other hand, when a p-typeInP substrate is used as the InP growth substrate 10, it can naturallybe understood that those layers have n-type and p-type conductivitytypes in reverse order. Further, when an undoped InP substrate is usedas the InP growth substrate 10, the conductivity type of those layersmay be determined to correspond to the conductivity (p-type or n-type)of the semiconductor layers formed on the InP growth substrate 10.

First Embodiment: Semiconductor Light-Emitting Diode

The semiconductor light-emitting diode 100 according to the firstembodiment of this disclosure can be fabricated by the manufacturingmethod of the above embodiment. The semiconductor light-emitting diode100 is a vertical semiconductor light-emitting diode 100 which operateswhen electric current flows in a vertical direction. Specifically, asillustrated in Step 4A of FIG. 4, this semiconductor light-emittingdiode 100 has the conductive support substrate 80; the metal bondinglayer 70 provided on the surface of the conductive support substrate 80;the reflective metal layer 60 provided on the metal bonding layer 70;the semiconductor laminate 30 in which a plurality of InGaAsP-basedIII-V compound semiconductor layers containing at least In and P arestacked, provided on the metal reflective layer 60; and the dielectriclayer 50 and the contact portion 40 which are provided in parallelbetween the reflective metal layer 60 and the semiconductor laminate 30.The main component of the reflective metal layer 60 is Au, and theconductive support substrate 80 is formed from a conductive Sisubstrate.

As described above, this semiconductor light-emitting diode 100 uses aconductive Si substrate as the conductive support substrate 80, so thatthe thickness of the support substrate can be made sufficiently small.Moreover, the semiconductor light-emitting diode 100 is also useful inthat the directivity of the emitted light is higher than in the case ofconventional semiconductor light-emitting diodes, since the reflectivemetal layer 60 is provided on the Si substrate side.

Further, in this embodiment, the thickness of the conductive supportsubstrate 80 can be 80 μm or more and less than 200 μm, and thethickness can be 150 μm or less, or 100 μm or less.

Preferably, the semiconductor laminate 30 includes an n-type claddinglayer 31, an active layer 35, and a p-type cladding layer 37 in thisorder, and the n-type cladding layer 31, the active layer 35, and thep-type cladding layer 37 are layers formed of an InGaAsP-based III-Vcompound semiconductor containing at least In and P. Also as describedabove, the semiconductor laminate 30 may have a double hetero structurein which the active layer 35 is sandwiched between the n-type claddinglayer 31 and the p-type cladding layer 37 or a multiple quantum wellstructure, and the active layer 35 preferably has multiple quantum wellstructure. The dielectric layer is preferably formed of SiO₂.

As described in the embodiment of the manufacturing method, thesemiconductor light-emitting diode 100 may have another optionalstructure. Further, as illustrated in Step 4B of FIG. 4, the backelectrode 91 and the top electrode 93 may be provided on thesemiconductor light-emitting diode 100 to obtain the semiconductorlight-emitting diode 100′.

Second Embodiment: Semiconductor Light Receiving Device

A method of manufacturing a semiconductor optical device and asemiconductor optical device according to this disclosure can be appliedto an embodiment of a semiconductor light receiving device. For example,when a semiconductor laminate including for example an InGaAs lightabsorption layer and an InP window layer is provided instead of thesemiconductor laminate 30 in the semiconductor light-emitting diode 100,the semiconductor optical device can be used as a semiconductor lightreceiving device. Since a semiconductor light receiving device accordingto this disclosure uses a Si substrate as a conductive supportsubstrate, as in the semiconductor light-emitting diode 100, thethickness of the conductive support substrate can be made small, andhence the total thickness of the semiconductor light receiving devicecan be made small; thus, a small semiconductor light receiving devicecan be obtained.

Third Embodiment: Method of Manufacturing Semiconductor Optical Device

Further, the use of a conductive support substrate formed from a Sisubstrate in a semiconductor optical device using a III-V compoundsemiconductor containing In and P, formed on an InP substrate accordingto this disclosure, can of course be applied to the following method ofmanufacturing a semiconductor optical device of the third embodiment.

As illustrated in FIG. 6, a method of manufacturing a semiconductoroptical device 1 according to the third embodiment of this disclosureincludes a step of forming the semiconductor laminate 30 in which aplurality of InGaAsP-based III-V compound semiconductor layerscontaining at least In and P are stacked, on the InP growth substrate(Steps 6A and 6B of FIG. 6); a step of bonding the semiconductorlaminate 30 to the conductive support substrate 80 formed from a Sisubstrate, with at least the metal bonding layer 70 therebetween (Step6C of FIG. 6); and a step of removing the InP growth substrate 10 (Step6D of FIG. 6).

Since the semiconductor optical device 1 uses a Si substrate as theconductive support substrate 80, the semiconductor optical device 1 canbe made smaller than conventional semiconductor optical devices using anInP growth substrate as a conductive support substrate. Hence, themanufacturing method according to this embodiment preferably furtherincludes a grinding step of grinding the conductive support substrate 80to a thickness in a range of 80 μm or more and less than 200 μm (Step 6Eof FIG. 6). Thus, the small semiconductor optical device 1′ can bemanufactured, in which the thickness of the conductive support substrate80 is in a range of 80 μm or more and less than 200 μm.

Third Embodiment: Semiconductor Optical Device

Further, the semiconductor optical device 1 of this disclosure can befabricated by the manufacturing method of the above embodiment.Specifically, as illustrated in Step 6D of FIG. 6, the semiconductoroptical device 1 of this disclosure has the conductive support substrate80 formed from a Si substrate; a metal bonding layer 70 provided on thesurface of the conductive support substrate 80; and the semiconductorlaminate 30 obtained by stacking a plurality of InGaAsP-based III-Vcompound semiconductor layers containing at least In and P are stacked,provided on the metal bonding layer 70.

Further, as illustrated in Step 6E of FIG. 6, the thickness of theconductive support substrate 80 is preferably in a range of 80 μm ormore and less than 200 μm. Thus, the semiconductor optical device 1′ canbe made small.

Note that in an embodiment of a semiconductor optical device and amethod of manufacturing the same according to the third embodiment, anygiven structure of the semiconductor light-emitting diode and thesemiconductor light receiving device according to the first embodimentand the second embodiment can be applied to the semiconductor opticaldevice 1 (1′).

EXAMPLES Example 1

The disclosed method of manufacturing a semiconductor optical devicewill be described in more detail below using examples. However, thisdisclosure is not limited to the following examples. A semiconductorlight-emitting diode of Example 1 was fabricated in accordance with theprocess steps illustrated in FIGS. 1 to 4. The steps are demonstrated asfollows.

First, on the (100) plane of an n-type InP substrate, an n-typeIn_(0.57)Ga_(0.43)As etch stop layer, an n-type InP cladding layer(thickness: 2 μm), an i-type InP spacer layer (thickness: 300 nm), anactive layer having a quantum well structure with an emission wavelengthof 1300 nm (130 nm in total), an i-type InP spacer layer (thickness: 300nm), a p-type InP cladding layer (thickness: 1.2 μm), a p-typeIn_(0.8)Ga_(0.20)As_(0.5)P_(0.5) cap layer (thickness: 50 nm), and ap-type In_(0.57)Ga_(0.43)As contact layer (thickness: 130 nm) weresequentially formed by MOCVD. Note that in forming the active layerhaving a quantum well structure, ten In_(0.73)Ga_(0.27)As_(0.5)P_(0.5)well layers (thickness: 5 nm) and ten InP barrier layers (thickness: 8nm) were alternately stacked.

On the p-type In_(0.57)Ga_(0.43)As contact layer, a p-type ohmicelectrode portion (Au/AuZn/Au, total thickness: 530 nm) was formed intoislands distributed as illustrated in FIG. 7A. The cross-sectional viewof FIG. 7A taken along line I-I corresponds to the schematiccross-sectional view of Step 2A in FIG. 2. When forming this pattern, aresist pattern was formed and an ohmic electrode was then vapordeposited, followed by lift-off of the resist pattern. When thesemiconductor layer of the wafer in this state was observed in a topview using an optical microscope, the contact area ratio of the p-typeohmic electrode portion with respect to the semiconductor layer was4.5%. Note that the outer size of the object depicted in FIG. 7A is 380μm square.

Next, a resist mask was formed on and around the p-type ohmic electrodeportion, and the p-type In_(0.57)Ga_(0.43)As contact layer was removed,except for areas where the ohmic electrode portion was formed, by wetetching using tartaric acid-hydrogen peroxide mixture. After that, adielectric layer (thickness: 700 nm) made of SiO₂ was formed on theentire surface of the p-type In_(0.80)Ga_(0.20)As_(0.50)P_(0.50) caplayer by plasma CVD. A window pattern having a shape extending over 3 μmeach in the width direction and the longitudinal direction in an areaabove the p-type ohmic electrode portion was formed using resist, andthe dielectric layer on and around the p-type ohmic electrode portionwas removed by wet etching using BHF to expose the p-typeIn_(0.80)Ga_(0.20)As_(0.50)P_(0.50) cap layer. At this time, the heightH₁ (700 nm) of the dielectric layer on the p-typeIn_(0.80)Ga_(0.20)As_(0.50)P_(0.50) cap layer is larger than the heightH₂ (660 nm) of the contact portion composed of the p-type contact layer(thickness: 130 nm) and the p-type ohmic electrode portion (thickness:530 nm) by 40 nm. When the semiconductor layer of the wafer in thisstate was observed in a top view using an optical microscope, thecontact area ratio of the dielectric layer (SiO₂) was 90%.

Next, a reflective metal layer (Al/Au/Pt/Au) was formed on the entiresurface of the p-type In_(0.80)Ga_(0.20)As_(0.50)P_(0.50) cap layer byvapor deposition. The thickness of the metal layers in the reflectivemetal layer was 10 nm, 650 nm, 100 nm, and 900 nm in this order.

On the other hand, a metal bonding layer (Ti/Pt/Au) was formed on aconductive Si substrate serving as a support substrate (thickness: 300μm). The thickness of the metal layers in the metal bonding layer was650 nm, 10 nm, and 900 nm in this order.

The reflective metal layer and the metal bonding layer were placed toface one another and were subjected to thermocompression bonding at 300°C. Further, the InP substrate was removed by wet etching using ahydrochloric acid diluent, and the n-type In_(0.57)Ga_(0.43)As etch stoplayer was removed by wet etching using sulfuric acid-hydrogen peroxidemixture.

Next, on the n-type InP cladding layer, an n-type electrode (Au(thickness: 10 nm)/Ge (thickness: 33 nm)/Au (thickness: 57 nm)/Ni(thickness: 34 nm)/Au (thickness: 800 nm)/Ti (thickness: 100 nm)/Au(thickness: 1000 nm)) was formed as a wiring portion of a top electrodeby resist pattern formation, vapor deposition of an n-type electrode,and lift-off of the resist pattern as illustrated in FIG. 7B. Further, apad portion (Ti (thickness: 150 nm)/Pt (thickness: 100 nm)/Au(thickness: 2500 nm)) was formed on the n-type electrode to obtain thetop electrode having a pattern as illustrated in FIG. 7B. Thecross-sectional view of FIG. 7B taken along line II-II corresponds toStep 4B in FIG. 4. Note that the outer size of the object depicted inFIG. 7B is 380 μm square as with FIG. 7A.

Finally, the semiconductor layers between devices (width: 60 μm) wereremoved by mesa etching to form dicing lines. A back electrode (Ti(thickness: 10 nm)/Pt (thickness: 50 nm)/Au (thickness: 200 nm)) wasformed on the back surface of the Si substrate, and chip singulation wasperformed by dicing to obtain a semiconductor light-emitting diode ofExample 1. The chip size was 350 μm×350 μm.

Example 2

A semiconductor light-emitting diode according to Example 2 wasfabricated in the same manner as in Example 1 except that the Sisubstrate was ground to a thickness of approximately 87 μm immediatelybefore forming the back electrode on the Si substrate to obtain asemiconductor light-emitting diode having a total thickness of 120 μm.

Conventional Example 1

A semiconductor light-emitting diode according to Conventional Example 1was fabricated as follows. First, on the (100) plane of an n-type InPsubstrate, an n-type InP cladding layer (thickness: 2 μm), an i-type InPspacer layer (thickness: 300 nm), an active layer having a quantum wellstructure with an emission wavelength of 1300 nm (130 nm in total), ani-type InP spacer layer (thickness: 300 nm), a p-type InP cladding layer(thickness: 1.2 μm), a p-type In_(0.80)Ga_(0.20)As_(0.50)P_(0.50) caplayer (thickness: 50 nm), and a p-type In_(0.57)Ga_(0.43)As contactlayer (thickness: 130 nm) were sequentially formed by MOCVD. A backelectrode (Ti (thickness: 10 nm)/Pt (thickness: 50 nm)/Au (thickness:200 nm)) was formed on the back surface of the n-type InP substrate, atop electrode (AuGe/Ni/Au electrode) was formed on a center portion ofthe p-type In_(0.57)Ga_(0.43)As contact layer, and singulation wasperformed as in Example 1. Note that in forming the active layer havinga quantum well structure, ten In_(0.73)Ga_(0.27)As_(0.50)P_(0.50) welllayers (thickness: 5 nm) and ten InP barrier layers (thickness: 8 nm)were alternately stacked.

Comparative Example 1

In Conventional Example 1, a semiconductor light-emitting diode wasfabricated in the same manner as in Conventional Example 1 except that aInP substrate was ground immediately before forming a back electrode onan InP substrate. However, the InP substrate was broken in the grindingbefore the thickness of the InP substrate reached 150 μm and the devicewas not completed in Comparative Example 1.

<Evaluation 1: Grinding Tolerance Evaluation>

As can be seen from the comparison between Example 1 and Example 2, whena Si substrate was used as the conductive support substrate, thesemiconductor light-emitting diode having a total thickness of 120 μmwas obtained by grinding the Si substrate, thus a small semiconductorlight-emitting diode with a center emission wavelength of 1300 nm wasobtained. On the other hand, as can be seen from the comparison betweenConventional Example 1 and Comparative Example 1, since the InPsubstrate was broken while being ground, thus a small semiconductorlight-emitting diode was not obtained.

<Evaluation 2: Light Distribution Characteristics Evaluation>

An electric current of 20 mA was flown to each semiconductorlight-emitting diode obtained in Example 1 and Conventional Example 1,and a light distribution pattern was identified using aspectrophotometer. Note that the identification was performed while thesemiconductor light-emitting diode was rotated 180° with a solid angleof 6×10⁻³ steradians and the distance between the semiconductorlight-emitting diode and the spectrophotometer was 20 cm. The lightdistribution patterns of Example 1 and Conventional Example 1 arepresented in FIGS. 8A and 8B, respectively. As seen from FIGS. 8A and8B, higher directivity was achieved in Example 1 than in ConventionalExample 1.

<Evaluation 3: Light Output Power Evaluation>

The forward voltage Vf at a 20 mA current supplied to each of thesemiconductor light-emitting diodes obtained in Example 1 andConventional Example 1 by a constant current constant voltage powersupply was measured and the light output power Po thereof was measuredusing an integrating sphere. The measurement was performed on threesamples for each example, and the average of the measurement results foreach example was calculated. The results are given in Table 1. The peakemission wavelength was measured using a fiber optic spectrometer inExample 1 and Conventional Example 1 and was in a range of 1290 nm to1310 nm in each example.

TABLE 1 Light output power Forward voltage Po (mW) Vf (V) Example 1 1.971.01 Conventional Example 1 0.56 1.04

The above results confirmed that a small semiconductor light-emittingdiode can be embodied with the use of a Si substrate in accordance withExamples 1 and 2 meeting the conditions of this disclosure. Further,since the reflective metal layer is used, Examples 1 and 2 are moreadvantageous than Conventional Example 1 in terms of achieving highdirectivity. Further, comparison of Example 1 and Conventional Example 1confirmed that the light output power was substantially increased whilethe forward voltage was slightly reduced in Example 1, as compared withConventional Example 1.

INDUSTRIAL APPLICABILITY

This disclosure advantageously provides a method of manufacturing asemiconductor optical device, which makes it possible to reduce thethickness of a semiconductor optical device including InGaAsP-basedIII-V compound semiconductor layers containing at least In and P to athickness smaller than that of conventional devices, and provides asemiconductor optical device. In particular, for a semiconductorlight-emitting diode, high directivity and substantially increased lightoutput power can be achieved, thus, the diode can be used as ahigh-performance semiconductor light-emitting diode.

REFERENCE SIGNS LIST

-   -   1, 1′: Semiconductor optical device    -   10: InP growth substrate    -   20: Etch stop layer    -   30: Semiconductor laminate    -   31: N-type cladding layer    -   35: Active layer    -   35W: Well layer    -   35B: Barrier layer    -   37: P-type cladding layer    -   39: P-type cap layer    -   40: Contact portion    -   41 (41 a): P-type contact layer    -   43: Ohmic metal portion    -   50: Dielectric layer    -   60: Reflective metal layer    -   70: Metal bonding layer    -   80: Support substrate (Conductive support substrate)    -   100, 100′: Semiconductor light-emitting diode    -   91: Back electrode    -   93: Top electrode    -   E1: Exposed area    -   E2: Exposed surface    -   E3: Exposed portion

1. A method of manufacturing a semiconductor optical device, comprising:a step of forming a semiconductor laminate in which a plurality ofInGaAsP-based III-V compound semiconductor layers containing at least Inand P are stacked, on an InP growth substrate; a step of bonding thesemiconductor laminate to a conductive support substrate formed from aSi substrate with at least a metal bonding layer therebetween; and astep of removing the InP growth substrate.
 2. The method ofmanufacturing a semiconductor optical device, according to claim 1,further comprising a grinding step of grinding the conductive supportsubstrate to a thickness in a range of 80 μm or more and less than 200μm.
 3. A method of manufacturing a semiconductor optical device,comprising: a first step of forming a semiconductor laminate in which aplurality of InGaAsP-based III-V compound semiconductor layerscontaining at least In and P are stacked, on an InP growth substrate; asecond step of forming a contact layer formed of a III-V compoundsemiconductor on the semiconductor laminate; a third step of forming anohmic metal portion on part of the contact layer leaving an exposed areaon a surface of the contact layer; a fourth step of removing the contactlayer of the exposed area so that a surface of the semiconductorlaminate is exposed, thereby forming a contact portion composed of theohmic metal portion and the contact layer and forming an exposed surfaceof the semiconductor laminate; a fifth step of forming a dielectriclayer on at least part of the exposed surface of the semiconductorlaminate; a sixth step of forming a reflective metal layer mainlycontaining Au on the dielectric layer and the contact portion; a seventhstep of bonding a conductive support substrate having a surface providedwith a metal bonding layer to the reflective metal layer with the metalbonding layer therebetween; and an eighth step of removing the InPgrowth substrate, wherein the support substrate is a conductive Sisubstrate.
 4. The method of manufacturing a semiconductor opticaldevice, according to claim 3, further comprising a grinding step ofgrinding the conductive support substrate to a thickness in a range of80 μm or more and less than 200 μm.
 5. The method of manufacturing asemiconductor optical device, according to claim 3, wherein thesemiconductor laminate includes an n-type cladding layer, an activelayer, and a p-type cladding layer in this order, and the n-typecladding layer, the active layer, and the p-type cladding layer arelayers formed of an InGaAsP-based III-V compound semiconductorcontaining at least In and P.
 6. The method of manufacturing asemiconductor optical device, according to claim 5, wherein thesemiconductor laminate has one of a double heterostructure and amultiple quantum-well structure.
 7. The method of manufacturing asemiconductor optical device, according to claim 3, wherein thedielectric layer is formed of SiO₂.
 8. A semiconductor optical devicecomprising: a conductive support substrate formed from a Si substrate; ametal bonding layer provided on a surface of the support substrate; anda semiconductor laminate in which a plurality of InGaAsP-based III-Vcompound semiconductor layers containing at least In and P are stacked,the semiconductor laminate being provided on the metal bonding layer. 9.The semiconductor optical device according to claim 8, wherein athickness of the conductive support substrate is in a range of 80 μm ormore and less than 200 μm.
 10. A semiconductor optical devicecomprising: a conductive support substrate; a metal bonding layerprovided on a surface of the conductive support substrate; a reflectivemetal layer provided on the metal bonding layer; a semiconductorlaminate in which a plurality of InGaAsP-based III-V compoundsemiconductor layers containing at least In and P are stacked, thesemiconductor laminate being provided on the reflective metal layer; anda dielectric layer and a contact portion that are provided in parallelbetween the reflective metal layer and the semiconductor laminate, thereflective metal layer mainly contains Au, and the conductive supportsubstrate is formed from a conductive Si substrate.
 11. Thesemiconductor optical device according to claim 10, wherein a thicknessof the conductive support substrate is in a range of 80 μm or more andless than 200 μm.
 12. The semiconductor optical device according toclaim 10, wherein the semiconductor laminate includes an n-type claddinglayer, an active layer, and a p-type cladding layer in this order, andthe n-type cladding layer, the active layer, and the p-type claddinglayer are layers formed of an InGaAsP-based III-V compound semiconductorcontaining at least In and P.
 13. The semiconductor optical deviceaccording to claim 12, wherein the semiconductor laminate has one of adouble heterostructure and a multiple quantum-well structure.
 14. Thesemiconductor optical device, according to claim 10, wherein thedielectric layer is formed of SiO₂.